XR88C681_06 Datasheet, PDF (61/101 Pages) Exar Corporation – CMOS Dual Channel UART (DUART)

XR88C681
2. Externally connect the OP3 pin to the IP3 and IP4 pins.
Thereby applying a 1 MHz square wave into these two
input pins.
3. Write FF₁₆ to CSRA.
This step will specify that the timing source for the
Transmitter and Receiver of Channel A will be derived
from input pins IP3 and IP4, respectively. Additionally,
this step allow the DUART hardware to presume that
these input signal are 1X signals. Hence, there is no
division-by-16 of this signal. Therefore, the bit rate of
Channel A is at 1 Mbps.
Please note that if the user were to apply this example,
he/she would be responsible for ensuring that the
incoming serial data stream is synchronous with the 1
MHz (1X) clock signal; in order to minimize bit errors.
D.7 Explanation of Clock Timing Signals
The purpose of this section is to explain the Data Sheet
specification on the Timing Control Block parameters. In
the past, this subject has been the source of considerable
confusion by numerous users.
The XR88C681 Data Sheet presents the following
parameter specifications in the
“AC ELECTRICAL CHARACTERISTICS”
Symbol
t_CLK
f_CLK
t_CTC
f_CTC
t_RTX
f_RTX
f_RTX - 16X
f_RTX - 1X
Parameter
Min.
X1/CLK (External) High or Low Time
100
X1/CLK Crystal or External Frequency
2.0
Counter/Timer External Clock High or Low
100
Time - IP2 Input
Counter/Timer External Clock Frequency - IP2
0
Input
RXC and TXC (External) High or Low Time -
220
via IP2, IP3, IP4 and IP5
RXC and TXC (External) Frequency - via IP2,
IP3, IP4, and IP5
16X
0
1X
0
Typ.
3.6864
Max.
4.0
4.0
2.0
1.0
Units
ns
MHz
ns
MHz
ns
MHz
MHz
Table 20. Clock Timing (Figure 13)
Now, here is an explanation for each of these parameters.
D t_CLK - X1/CLK (External) High or Low Time
The DUART employs dynamic logic throughout much of
its circuitry. Therefore, limits on tCLK and fCLK are
needed in order to ensure that the device will function
properly. This parameter just places a lower limit on the
amount of time at the signal applied through the X1/CLK
pin must reside at the high and low states.
D f_CLK - X1/CLK Crystal High or Low Time
This parameter specifies the range of frequencies
permissible at the X1/CLK input, via either crystal
oscillator or applied TTL input signal. Therefore, the use
can only apply between 2.0 and 4.0 MHz at this input.
D t_CTC - Counter/Timer External Clock High or Low
Time - IP2 Input
This parameter places a lower limit on the amount of time
that the signal, being applied to the IP2 pin, for use by the
Counter/Timer, can reside at the high and low states.
Please note that this limit has no relationship with the
parameter tRTX, which is another spec associated with
the IP2 input.
D f_CTC - Counter/Timer External Clock Frequency -
IP2 Input
This parameter places an upper limit of the input
frequency being applied to the IP2 pin, for use by the
Counter/Timer. The spec basically states that a signal
with frequency up to 4.0 MHz can be applied at the IP2
pin, and still be properly handled by the Counter/Timer.
Rev. 2.11
61