XR88C681_06 Datasheet, PDF (5/101 Pages) Exar Corporation – CMOS Dual Channel UART (DUART)

XR88C681
44 PLCC
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
40 PDIP,
CDIP
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
28 PDIP
Symbol
Type Description
9
OP1
O Output 1 (General Purpose Output). This output can also
(-RTSB)
be programmed to function as the active-low, “Channel B
Request-to-Send” Output (-RTSB).
OP3
O Output 3 (General Purpose Output). This output port can
(TXCB_1X)
also be programmed to function as: the “Channel B Trans-
(RXCB_1X)
mitter 1X clock” output (TXCB_1X), the “Channel B Receiv-
(-C/T_RDY)
er 1X clock” output (RXCB_1X), or the open drain, active-
low “Counter/Timer Ready” output (-C/T_RDY).
OP5
O Output 5 (General Purpose Output Pin). This output port
(-RXRDY/
pin can also be programmed to function as the open-drain,
-FFULL_B)
active-low, Channel B “Receive Ready” or “Receiver FIFO
Full” indicator output (-RXRDY_B/-FFULL_B).
OP7
O Output 7. (General Purpose Output Pin). This output port
(TXRDY_B)
pin can also be programmed to function as the open-drain,
active-low, “Transmitter Ready” indicator output for Channel
B (-TXRDY_B).
10
D1
I/O Bi-Directional Data Bus.
11
D3
I/O Bi-Directional Data Bus.
12
D5
I/O Bi-Directional Data Bus.
13
D7
I/O MSB of the Eight Bit Bi-Directional Data Bus. All transfers
between the CPU and the DUART take place over this bus
(consisting of pins D0 - D7). The bus is tri-stated when the
-CS input is “high”, except during an IACK cycle (in the Z-
Mode).
14
GND
PWR Signal Ground.
NC
No Connect.
15
-INTR
O Interrupt Request Output (Active Low, Open Drain).
-INTR is asserted upon the occurrence of one or more of the
chip’s maskable interrupting conditions. This signal will re-
main asserted throughout the Interrupt Service Routine and
will be negated once the condition(s) causing the Interrupt
Request has been eliminated.
16
D6
I/O Bi-Directional Data Bus.
17
D4
I/O Bi-Directional Data Bus.
18
D2
I/O Bi-Directional Data Bus.
19
D0
I/O LSB of the Eight Bit Bi-Directional Data Bus. All transfers
between the CPU and the DUART take place over this bus.
The bus is tri-stated when the -CS input is “high”, except
during an IACK cycle (in the Z-Mode).
OP6
O Output 6 (General Purpose Output). This output pin can
(-TXRDY_A)
also be programmed to function as the open drain, active-
low, “Transmitter Ready” indicator output for Channel A
(-TXRDY_A).
Rev. 2.11
5