XR88C681_06 Datasheet, PDF (40/101 Pages) Exar Corporation – CMOS Dual Channel UART (DUART)

XR88C681
V_CC
-INT
CPU
V_CC
-INTR
IEI
IEO
-IACK
-INTR
IEI
IEO
-IACK
-INTR
IEI
IEO
-IACK
-INTR
IEI
IEO
-IACK
-IACK
HIGHEST
PRIORITY
LOWEST
Figure 15. A Diagram of Numerous DUARTs Configured in an Interrupt
Daisy Chain (for Z-Mode Operation)
In addition to the -INTR and -IACK pins, the Z-Mode
DUART also uses the IEI and IEO pins; which are defined
as follows:
IEI - Interrupt Enable Input
This active-high input is only available if the DUART is
configured to operate in the Z-Mode. If this input is at a
logic “high” then all unmasked interrupt requests, from
this DUART, are enabled.
Note:
Those interrupts which have been masked out by the IMR are
still disabled. However, if this input is at a logic “low”, then all
interrupts (whether masked or unmasked) are disabled.
Hence, IEI can act to globally disable all DUART interrupt
requests.
IEO - Interrupt Enable Output
This active-high output is only available if the DUART is
configured to operate in the Z-Mode. This output is often
times connected to the IEI input of another (lower priority)
device. This output is “high” if all of the following
conditions are true.
D The device’s IEI input is at a logic “high”
D The device is not requesting an interrupt from the
CPU
D An interrupt, requested by the device, has just been
serviced
If any of these conditions are false, then the IEO pin will be
at a logic “low”.
Note:
Once the IEO pin has toggled “low”, and the CPU has ac-
knowledged the interrupt request and has completed the inter-
rupt service routine, the IEO pin will remain “low” until the user
invokes the “RESET IUS” command (see Table 3). Therefore,
if the DUART is going to operate in the Z-Mode, the user must
include the “RESET IUS” Command at the very end of the
DUART interrupt service routine.
System Level Application of the IEI and IEO pins
Figure 15 depicts a series of DUARTs connected in a
daisy-chain fashion. In this figure, the left-most DUART
has the highest interrupt priority. This is because this
DUART’s IEI input is hardwired to Vcc. Therefore, the
unmasked interrupt requests, from this DUART are
always enabled. The DUART device, located just to the
right of the “highest interrupt priority” device is of a lower
interrupt priority. This is because the IEI input of this lower
priority device is connected to the IEO output of the
highest priority DUART. Whenever the “highest priority”
device requests an interrupt, its IEO output will toggle
“low”. This will in turn, disable the “lower priority” device
Rev. 2.11
40