XR88C681_06 Datasheet, PDF (19/101 Pages) Exar Corporation – CMOS Dual Channel UART (DUART)

XR88C681
C. INTERRUPT CONTROL BLOCK
The Interrupt Control Block allows the user to apply the
DUART in an “Interrupt Driven” environment. The
DUART includes an interrupt request output signal
(-INTR), which may be programmed to be asserted upon
the occurrence of any of the following events:
D Transmit Hold Register A or B Ready
D Receive Hold Register A or B Ready
D Receive FIFO A or B Full
D Start or End of Received Break in Channels A or B
D End of Counter/Timer Count Reached
D Change of State on input pins, IP0, IP1, IP2, IP3
The Interrupt Control Block consists of an Interrupt Status
Registers (ISR), an Interrupt Mask Registers (IMR), a
Masked Interrupt Status Registers (MISR) and an
Interrupt Vector Register (IVR). Table 4 lists these
registers, their address location (within the DUART).
Register
ISR
IMR
MISR
IVR
Description
Interrupt Status Register
Interrupt Mask Register
Masked Interrupt Status Register
Interrupt Vector Register
Address Location
(in DUART Address Space)
05₁₆ (Read Only)
05₁₆ (Write Only)
02₁₆ (Read Only)
0C₁₆
Table 4. Listing and Brief Description of Interrupt System Registers
The role and purpose of each of these registers are
defined here.
C.1 Interrupt Status Registers (ISR)
The contents of the ISR indicates the status of all potential
interrupt conditions. If any bits within these registers are
toggled “high”, then the corresponding condition has or is
occurring. In general, the contents of the ISR will indicate
to the processor, the source or the reason for the Interrupt
Request from the DUART. Therefore, any interrupt
service routine for the DUART should begin by reading
either this register or the MISR (Masked Interrupt Status
Register). The bit-format of the ISR is presented in
Table 5:
Bit 7
Input Port
Change
0 = No
1 = Yes
Bit 6
Delta Break
B
0 = No
1 = Yes
Bit 5
RXRDY/
FFULLB
0 = No
1 = Yes
Bit 4
TXRDYB
0 = No
1 = Yes
Bit 3
Counter
Ready
0 = No
1 = Yes
Bit 2
Delta Break
A
0 = No
1 = Yes
Bit 1
RXRDY/
FFULLA
0 = No
1 = Yes
Bit 0
TXRDYA
0 = No
1 = Yes
Table 5. ISR Bit Format
The definition of the meaning behind each of these bits is
presented here.
ISR[7]: Input Port Change of State
If this bit is at a logic “1”, then a change of state was
detected at Input Port pins IP0 - IP3. The user would
service this interrupt by reading the IPCR (if ISR[7] = 1).
ISR[7] is cleared when the CPU has read the Input Port
Configuration Register (IPCR). By reading the IPCR, the
user will determine:
D The individual Input Port pin that changed state
D The final state of the monitored input ports, following
the Change of State.
For a detailed description of the IPCR, see Section F.
Please note that in order to enable this Interrupt
Condition, the user must do two things:
1. Write the appropriate data to the lower nibble of the
Auxiliary Control Register, ACR[3:0]. In this step, the
user is specifying which Input Pins should trigger an
“Input Port Change” Interrupt request.
Rev. 2.11
19