XR88C681_06 Datasheet, PDF (71/101 Pages) Exar Corporation – CMOS Dual Channel UART (DUART)

XR88C681
Receiver Errors
If the Receiver does not sample a “mark”, at the presumed
time of the STOP bit, a Framing Error (FE) is flagged by
setting, SRn[6] =1. If, upon complete reception of the
character, the subsequent parity check is incorrect, a
Parity Error (PE) is flagged by setting SRn[5] = 1. If the
RHR was full, and another character existed in the RSR;
and if more data enters the DUART via the corresponding
RXDn pin; then the character in the RSR will be
overwritten, and a Receiver Overrun Error (OE) condition
will be flagged in the Status Register (SRn[4] = 1). This
phenomenon obviously results in a loss of data.
Finally if the RXDn input is held at the space condition for
an entire character period, and no STOP bit was detected
(STOP bit sampling resulted in a space); a Received
Break (RB) condition is presumed. When this condition is
detected several things happen.
1. The “Received Break” condition is flagged in the
Status Register (SRn[7] = 1).
2. The “Break” character is loaded into the RHR.
However, no further data is received or loaded into the
RHR until the RXDn input returns to the “mark”
condition.
3. The corresponding “Delta Break” interrupt is
requested (if programmed) and flagged in the Interrupt
Status register.
Once the RXDn input returns to the “mark” condition,
subsequent characters will be loaded into the RHR, and
the corresponding “Delta Break” interrupt condition will
once again be requested (if programmed) and flagged in
the Interrupt Status Register.
The DUART can be programmed to generate an Interrupt
Request to the CPU if a RXRDY (Receiver Ready) or a
FFULL (FIFO Full) Condition exists for either channel. A
RXRDY Condition exists when at least one character of
data exists within the RHR, and is ultimately waiting to be
“popped” and read by the CPU. The FFULL condition
exists when the RHR is completely full and cannot accept
any new characters from the RSR until the CPU has read
or “popped” the FIFO. The user can select the Interrupt
Request to occur due to either (but not both) the RXRDY
or FFULL condition via the Channel Mode Registers.
These interrupts are enabled by setting IMR[1] and
IMR[5] for Channels A and B, respectively.
Each channel is equipped with numerous other registers
that are used to provide control and monitoring of these
channels. Some of these registers were discussed in
earlier sections of the data sheet. However, a detailed
discussion of the remainder of these registers are
presented in Section G.3.
G.3 Mode Registers, MR1n and MR2n
The Mode Registers, allow the user to specify of the
protocol parameters that he/she wish the channel to run
at. These registers also allow the user to configure the
DUART channels to engage in modem handshaking
techniques. The bits of each of these registers are
discussed in Table 26.
Bit 7
Rx RTS
Control
0 = No
1 = Yes
Bit 6
Rx Interrupt
Select
0=RxRDY
1=FFULL
Bit 5
Error Mode
0=Character
1= Block
Bit 4
Bit 3
Parity Mode
Select
00 = With Parity
01 = Force Parity
10 = No Parity
11 = Multi-Drop Mode
Bit 2
Select
Parity
0 = Even
1 = Odd
Bit 1
Bit 0
Select Number of Bits per
Character
00 = 5
01 = 6
10 = 7
11 = 8
Note: MR1n for each channel is accessed when the channel’s MR pointer points to MR1. The pointer is set to MR1n by a hardware
RESET or by a “RESET MR POINTER” command invoked via the channel’s command register. After any read or write to
MR1, the MR pointer will automatically point to MR2.
Rev. 2.11
Table 26. Mode Registers - MR1A, MR1B
71