XR88C681_06 Datasheet, PDF (4/101 Pages) Exar Corporation – CMOS Dual Channel UART (DUART)

XR88C681
PIN DESCRIPTION
44 PLCC
1
2
40 PDIP,
CDIP
1
3
2
4
3
5
4
6
5
7
6
8
7
9
8
10
9
11
10
12
13
11
28 PDIP Symbol Type Description
NC
No Connection.
1
A0
I
LSB of Address Input. This input, along with Address Inputs,
A1 - A3 are used to select certain registers within the DUART
device, during READ and WRITE operations with the CPU.
IP3
I
Input Port 3. General Purpose Input - When the DUART is
(TXCA - I)
operating in the I-mode, this input can also be used as the
(RXCA - Z)
external clock input for the Channel A Transmitter (TXCA).
When the DUART is operating in the Z-Mode, this input can
be used as the external clock input for the Channel A Receiv-
er (RXCA).
2
A1
I
Address Input.
IP1
(-CTSB)
I
Input Port 1. General Purpose Input - This input can also be
used as the Active Low, “Channel B Clear to Send” input.
(-CTSB)
3
A2
I
Address Input.
4
A3
I
MSB of Address Input. This input, along with Address In-
puts, A0 - A2 are used to select certain registers within the
DUART device, during READ and WRITE operations with the
CPU.
IP0
(-CTSA)
I
Input 0. General Purpose Input - This input can also be used
as the active-low, “Channel A Clear-to-Send” input. (-CTSA)
5
-WR
I
Write Strobe (Active-Low). A “low” on this input while -CS is
also “low” writes the contents of the Data Bus into the ad-
dressed register, within the DUART. The transfer occurs on
the rising edge of -WR.
6
-RD
I
Read Strobe (Active Low). A “low” on this input while -CS is
also “low” places the contents of the addressed DUART regis-
ter, on the data bus.
7
RXDB
I
Receive Serial Data Input (Channel B). The least significant
bit of the character is received first. If external receiver clock,
RXCB, is specified, the data is sampled on the rising edge of
this clock.
NC
No Connect.
8
TXDB
O Transmitter Serial Data Output (Channel B). The least sig-
nificant bit of the character is transmitted first. This output is
held in the high (marking state) when the transmitter is idle,
disabled, or when the channel is operating in the local LOOP-
BACK mode. If an external transmitter clock is specified,
TXCB, the transmitted data is shifted out of the TSR (Trans-
mitter Shift Register) on the falling the edge of this clock.
Rev. 2.11
4