XR88C681_06 Datasheet, PDF (21/101 Pages) Exar Corporation – CMOS Dual Channel UART (DUART)

XR88C681
one or two characters are still remaining in RHRA, following
data reception. Hence, it is possible that the last two char-
acters in a string of data (being received) could be lost due
to this phenomenon. Therefore, the user is advised to read
RHRA until empty.
ISR[0]: Channel A Transmitter Ready
This bit is a duplicate of TXRDY A, SRA[2].
This bit, when set, indicates that THRA is empty and is
ready to accept a character from the CPU. The bit is
cleared when the CPU writes a new character to THRA;
and is set again, when that character is transferred to the
TSR. TXRDYA is set when the transmitter is initially
enabled and is cleared when the transmitter is disabled.
Characters loaded into THRA while the transmitter is
disabled will not be transmitted.
C.2 Interrupt Mask Register (IMR)
The Interrupt Mask Register is a “Write Only” register
which enables the user to select the conditions that will
cause the DUART to issue an Interrupt Request to the
processor. In other words, the user has the option of
masking or blocking certain conditions from causing the
DUART to issue an Interrupt Request. Therefore, the
bit-format of the IMR is essentially the same as the ISR.
However, for completeness, the Bit Format of the IMR is
presented here.
Bit 7
Input Port
Change
0 = Off
1 = On
Bit 6
Delta Break
B
0 = Off
1 = On
Bit 5
RXRDY/
FFULLB
0 = Off
1 = On
Bit 4
TXRDYB
0 = Off
1 = On
Bit 3
Counter
Ready
0 = Off
1 = On
Bit 2
Delta Break
A
0 = Off
1 = On
Bit 1
RXRDY/
FFULLA
0 = Off
1 = On
Bit 0
TXRDYA
0 = Off
1 = On
Table 6. IMR Bit Format
If the user wishes to enable a certain interrupt, he/she
should write a “1” to the bit within the IMR, corresponding
to that Interrupt Condition. Likewise, to disable or mask
out a certain condition causing an interrupt, the user
should write a “0” to the bit location corresponding to that
condition. To enable all interrupts the user would write
FF₁₆ (all “1”s) to this registers.
Please note that IMR is a Write Only Registers, and can
therefore not be read by the processor.
C.3 Masked Interrupt Status Register (MISR)
The content of the MISR register is basically the results of
ANDing the ISR and IMR together.
MISR Content = [ISR Contents] ¯ [IMR Contents]
One limitation of DUART Interrupt Service Routines that
rely on reading the ISR is that the bits within the ISR can
toggle “high” due to their corresponding conditions
whether or not they are enabled by the IMR. Therefore,
the user, following reading the Interrupt Status Register,
will have to make provisions for; and execute a “bit-by-bit”
AND of the ISR and IMR contents. Since the IMR is a
“Write Only” register and cannot be read by the processor,
the contents of the IMR will have to be stored in system
memory, for later recall. The additional hardware and
software overhead required to support this activity can be
eliminated via use of the MISR.
C.4 Interrupt Vector Register, IVR
This register is only used for Interrupt Vector generation
when the DUART is commanded into the special Z-Mode.
While in this mode, the contents of the IVR is typically
related to the starting address of the DUARTs Interrupt
Service Routine. Otherwise, in the I-Mode, Interrupt
Vector generation is typically performed off-chip. When
the DUART is operating in the I-Mode, the IVR can be
used as general purpose read/write registers. The role of
the IVR, while the DUART is operating in the Z-Mode is
presented in Section C.6.
C.5 Limitations of the DUART Interrupt Structure
The Interrupt Structure offered by the DUART allows the
user to program the DUART to generate interrupts in
response to certain THR and RHR (FIFO) conditions; the
Counter/Timer Ready condition, and to changes in the
Break Condition (at the Receiver). However, aside from
the “Delta Break Condition” (RB), the DUART’s Interrupt
Structure does not allow for interrupt requests due to
Rev. 2.11
21