XR88C681_06 Datasheet, PDF (54/101 Pages) Exar Corporation – CMOS Dual Channel UART (DUART)

XR88C681
D.3 Counter/Timer
The Timing Control Block also contains a 16 bit
Counter/Timer (C/T). The C/T is a programmable 16 bit
down-counter which can use one of several timing
sources as its input. Figure 28 presents a block diagram
of the circuitry surrounding the C/T. The selection of these
timing sources for the Counter/Timer can be made by
writing the appropriate data to ACR[6:4] (Auxiliary Control
Register bits 6 through 4). Please see Table 16 for the
relationship between the Counter/Timer mode, the
Timing Source and ACR[6:4]. The C/T output is available
to the Clock Select Registers for use as a programmable
bit rate generator for both Transmitters and Receivers.
Oscillator
Circuit
Divide by 16
IP2
TXCA
TXCB
Divide by 16
Preset Registers
(CTUR, CTLR)
Counter/Timer
ACR[4-6]
to 32:1 MUXs
C/T_RDY
(OP3)
Figure 28. A Block Diagram of the Circuitry Associated with the
Counter/Timer
Bit 6
0
0
0
0
1
1
1
1
Bit 5
0
0
1
1
0
0
1
1
Bit 4
0
1
0
1
0
1
0
1
C/T Mode
Counter
Counter
Counter
Counter
Timer
Timer
Timer
Timer
Timing Source
External Input - IP2
TXCA 1X - Clock of Channel A Transmitter
TXCB 1X - Clock of Channel B Transmitter
X1/CLK Input Divided by 16
External Input - IP2
External Input - IP2, Divided by 16
X1/CLK Input
X1/CLK Input Divided by 16
Rev. 2.11
Table 16. ACR[6:4] Bit Field Definition - C/T
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