M13S128324A-2M Datasheet, PDF (9/48 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

ESMT
M13S128324A (2M)
AC Timing Parameter & Specifications (Note: 1~6, 9~10)
Parameter
-3.6
Symbol
Min Max
-4
Min Max
-5
Min Max
-6
Unit
Min Max
Note
CL2
7.5 12 7.5 12 7.5 12 7.5 12
Clock Period
CL2.5
t_CK
6.0 12 6.0 12 6.0 12 6.0 12 ns
CL3
3.6 12 4.0 12 5.0 12 6.0 12
DQ output access time from
CLK/ CLK
t_AC
-0.6 +0.6 -0.7 +0.7 -0.7 +0.7 -0.7 +0.7 ns
CLK high-level width
CLK low-level width
DQS output access time from
CLK/ CLK
t_CH
0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 t_CK
t_CL
0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 t_CK
t_DQSCK -0.6 +0.6 -0.7 +0.7 -0.7 +0.7 -0.7 +0.7 ns
Clock to first rising edge of DQS delay t_DQSS 0.8 1.2 0.8 1.2 0.8 1.2 0.8 1.2 t_CK
DQ and DM input setup time (to DQS) t_DS
0.4
0.45
0.45
0.45
ns
DQ and DM input hold time (to DQS)
DQ and DM input pulse width (for
each input)
Address and Control Input setup time
(fast slew rate)
Address and Control Input hold time
(fast slew rate)
Address and Control Input setup time
(slow slew rate)
Address and Control Input hold time
(slow slew rate)
Control and Address input pulse width
(for each input)
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CLK setup time
DQS falling edge hold time from CLK
t_DH
t_DIPW
t_IS
t_IH
t_IS
t_IH
t_IPW
t_DQSH
t_DQSL
t_DSS
t_DSH
0.4
0.45
0.45
0.45
1.75
1.75
1.75
1.75
0.9
0.9
1.0
1.0
0.9
0.9
1.0
1.0
1.0
1.0
1.1
1.1
1.0
1.0
1.1
1.1
2.2
2.2
2.2
2.2
0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6
0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
ns
ns
18
ns 15,17~19
ns 15,17~19
ns 16~19
ns 16~19
ns
18
t_CK
t_CK
t_CK
t_CK
Data strobe edge to output data edge t_DQSQ
0.4
0.4
0.4
0.45 ns
22
Data-out high-impedance time from
CLK/ CLK
t_HZ
-0.7 +0.7 -0.7 +0.7 -0.7 +0.7 -0.7 +0.7 ns
11
Data-out low-impedance time from
CLK/ CLK
Clock half period
DQ-DQS output hold time from DQS
Data hold skew factor
t_LZ
-0.7 +0.7 -0.7 +0.7 -0.7 +0.7 -0.7 +0.7 ns
t_CLmin
t_CLmin
t_CLmin
t_CLmin
t_HP
or
or
or
or
ns
t_CHmin
t_CHmin
t_CHmin
t_CHmin
t_QH
t_HP-
t_QHS
t_HP-
t_QHS
t_HP-
t_QHS
t_HP-
t_QHS
ns
t_QHS
0.4
0.45
0.45
0.5 ns
11
20,21
21
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2011
Revision : 1.3
9/48