M13S128324A-2M Datasheet, PDF (47/48 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

ESMT
M13S128324A (2M)
Revision History
Revision
0.1
0.2
1.0
1.1
1.2
1.3
Date
2009.12.10
2009.12.23
2010.03.05
2010.03.29
2010.05.27
2011.08.09
Description
Original
Delete CAS Latency 4
Delete “Preliminary”
Add package description into ball configuration
1. Modify the specification of t_DQSQ for -5
2. Distribute t_RCD into t_RCDRD and t_RCDWR
1. Add operating ambient temperature into absolute maximum
ratings
2. Correct Active/Precharge Power Down Mode of command
truth table
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2011
Revision : 1.3
47/48