M13S128324A-2M Datasheet, PDF(13/48 Page) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

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M13S128324A-2M Datasheet, PDF (13/48 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

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ESMT

M13S128324A (2M)

Basic Functionality

Power-Up and Initialization Sequence

DDR SDRAM must be powered up and initialized in a predefined manner. Operational procedures other than those specified may

result in undefined operation. No power sequencing is specified during power up and power down given the following criteria:

Â VDD and VDDQ are driven from a single power converter output, AND

Â VTT is limited to 1.35 V, AND

Â VREF tracks VDDQ /2

OR, the following relationships must be followed:

Â VDDQ is driven after or with VDD such that VDDQ < VDD + 0.3 V, AND

Â VTT is driven after or with VDDQ such that VTT < VDDQ + 0.3 V, AND

Â VREF is driven after or with VDDQ such that VREF < VDDQ + 0.3 V.

At least one of these two conditions must be met.

Except for CKE, inputs are not recognized as valid until after VREF is applied. CKE is an SSTL_2 input, but will detect an LVCMOS

LOW level after VDD is applied. Maintaining an LVCMOS LOW level on CKE during power-up is required to guarantee that the DQ

and DQS outputs will be in the High-Z state, where they will remain until driven in normal operation (by a read access).

After all power supply and reference voltages are stable, and the clock is stable, the DDR SDRAM requires a 200 Î¼s delay prior to

applying an executable command. Once the 200 Î¼s delay has been satisfied, a DESELECT or NOP command should be applied,

and CKE should be brought HIGH.

Following the NOP command, a PRECHARGE ALL command should be applied. Next a MODE REGISTER SET command should

be issued for the Extended Mode Register, to enable the DLL, and then a MODE REGISTER SET command should be issued for

the Mode Register, to reset the DLL, and to program the operating parameters. 200 clock cycles are required between the DLL reset

and any executable command. A PRECHARGE ALL command should be applied, placing the device in the âall banks idleâ state.

Once in the idle state, two AUTO refresh cycles must be performed. Additionally, a MODE REGISTER SET command for the Mode

Register, with the reset DLL bit deactivated (i.e., to program operating parameters without resetting the DLL) must be performed.

Following these cycles, the DDR SDRAM is ready for normal operation.

Elite Semiconductor Memory Technology Inc.

Publication Date : Aug. 2011

Revision : 1.3

13/48

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