M13S128324A-2M Datasheet, PDF (33/48 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

ESMT
Multi Bank Interleaving WRITE (@ BL=4)
0
1
CLK
CLK
2
3
CKE
4
5
HIGH
M13S128324A (2M)
6
7
8
9
10
CS
RAS
CAS
BA0,BA1
BAa
BAb
BAa
BAb
A8/AP
Ra
Rb
ADDR
(A0~An)
Ra
Rb
Ca
Cb
WE
DQS
DQ
DM
COMMAND
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3
ACTIVE
tRCDW R
ACTIVE
tRRD
tCCD
WRITE
tRCDW R
WRITE
: Don’t care
10122B32R.B1
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2011
Revision : 1.3
33/48