M13S128324A-2M Datasheet, PDF (27/48 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

ESMT
M13S128324A (2M)
Auto Refresh & Self Refresh
Auto Refresh
An auto refresh command is issued by having CS , RAS and CAS held low with CKE and WE high at the rising edge of the
clock (CLK). All banks must be precharged and idle for t_RP(min) before the auto refresh command is applied. No control of the
external address pins is requires once this cycle has started because of the internal address counter. When the refresh cycle has
completed, all banks will be in the idle state. A delay between the auto refresh command and the next activate command or
subsequent auto refresh command must be greater than or equal to the t_RFC(min).
A maximum of eight consecutive AUTO REFRESH commands (with t_RFC(min)) can be posted to any given DDR SDRAM meaning
that the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is 8 x t_REFI .
CLK
CLK
COMMAND
CKE = High
PRE
tRP
Auto
Refresh
tRFC
CMD
Self Refresh
A self refresh command is defines by having CS , RAS , CAS and CKE held low with WE high at the rising edge of the clock
(CLK). Once the self refresh command is initiated, CKE must be held low to keep the device in self refresh mode. During the self
refresh operation, all inputs except CKE are ignored. Since CKE is an SSTL_2 input, V_REF must be maintained during self refresh.
The clock is internally disabled during self refresh operation to reduce power consumption. The self refresh is exited by supplying
stable clock input before returning CKE high, asserting deselect or NOP command and then asserting CKE high for longer than t_XSRD
for locking of DLL.
CLK
CLK
COMMAND
NOP
Self
Refresh
CKE
tIS
NOP
NOP
NOP
NOP
tXSNR(min)
Auto
Refresh
NOP
tIS
Note: After self refresh exit, input an auto refresh command immediately.
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2011
Revision : 1.3
27/48