M13S128324A-2M Datasheet, PDF (40/48 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

ESMT
Read Interrupted by a Write & Burst Terminate (@ BL=8, CL=2)
0
1
CLK
CLK
CKE
2
3
4
5
6
HIGH
CS
RAS
CAS
BA0,BA1
BAa
BAb
A8/AP
ADDR
(A0~An)
Ca
Cb
WE
M13S128324A (2M)
7
8
9
10
DQS
DQ
DM
COMMAND
Qa0 Qa1
Db0 Db1 Db2 Db3 Db4 db5 Db6 Db7
READ
Burst
Terminate
WRITE
: Don’t care
10122B32R.B
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2011
Revision : 1.3
40/48