M13S128324A-2M Datasheet, PDF (39/48 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

ESMT
M13S128324A (2M)
Read Interrupted by Precharge (@ BL=8)
0
1
CLK
CLK
CKE
2
3
4
5
6
7
8
9
10
HIGH
CS
RAS
CAS
BA0,BA1
BAa
BAb
A8/AP
ADDR
(A0~An)
Ca
WE
DQS(CL=2)
DQ(CL=2)
DQS(CL=2.5)
DQ(CL=2.5)
2 tCK Valid
Qa0 Qa1 Qa2 Qa3 Qa4 Qa5
2.5 tCK Valid
Qa0 Qa1 Qa2 Qa3 Qa4 Qa5
DM
COMMAND
READ
PRE
CHARGE
: Don’t care
10122B32R.B
When a burst Read command is issued to a DDR SDRAM, a Precharge command may be issued to the same bank before the Read
burst is complete. The following functionality determines when a Precharge command may be given during a Read burst and when a
new Bank Activate command may be issued to the same bank.
1. For the earliest possible Precharge command without interrupting a Read burst, the Precharge command may be given on the
rising clock edge which is CL clock cycles before the end of the Read burst where CL is the CAS Latency. A new Bank Activate
command may be issued to the same bank after t_RP (RAS Precharge time).
2. When a Precharge command interrupts a Read burst operation, the Precharge command may be given on the rising clock edge
which is CL clock cycles before the last data from the interrupted Read burst where CL is the CAS Latency. Once the last data
word has been output, the output buffers are tri-stated. A new Bank Activate command may be issued to the same bank after
t_RP.
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2011
Revision : 1.3
39/48