M13S128324A-2M Datasheet, PDF(43/48 Page) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

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M13S128324A-2M Datasheet, PDF (43/48 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

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ESMT

Power up & Initialization Sequence (based on DDR400)

M13S128324A (2M)

VDD

VDDQ

VTT

(system*)

VREF

CLK

CKE

COMMAND

tVDT >=0

tCK

tCH tCL

tIS tIH

LVC OMS LO W LE VE L

tIS tIH

NOP

PRE

EMRS

MRS

PRE

MRS

ACT

A0-A7

A9-An

BA0, BA1

tIS tIH

ALL BANKS

tIS tIH

CODE

tIS tIH

CODE

tIH tIS

BA0=H,

BA1=L

CODE

tIS tIH

ALL BANKS

BA0=L,

BA1=L

CODE

BA0=L,

BA1=L

DQS

High-Z

T=200us

Power-up:

VDD and

CLK stable

tMRD

tRP

200 cycles of CLK**

Extended

Mode

Load

Set

Mode

Reset DLL

(with A8=H)

tRFC

tMRD

Load

Mode

(with A8=L)

: Donât care

10122B32R.B

Notes:

* = VTT is not applied directly to the device, however tVTD must be greater than or equal to zero to avoid device latch-up.

** = tMRD is required before any command can be applied, and 200 cycles of CLK are required before an executable command

can be applied. The two Auto Refresh commands may be moved to follow the first MRS but precede the second

PRECHARGE ALL command.

Elite Semiconductor Memory Technology Inc.

Publication Date : Aug. 2011

Revision : 1.3

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