M13S128324A-2M Datasheet, PDF (6/48 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

ESMT
M13S128324A (2M)
IDD Parameters and Test Conditions
Test Condition
Operating Current (one bank Active - Precharge):
t_RC = t_RC (min); t_CK = t_CK (min); DQ, DM, and DQS inputs changing once per clock cycle;
Address and control inputs changing once every two clock cycles; CS = high between valid commands.
Operating Current (one bank Active - Read - Precharge):
One bank open; BL = 4; t_RC = t_RC (min); t_CK = t_CK (min); I_OUT = 0mA;
Address and control inputs changing once per deselect cycle; CS = high between valid commands
Precharge Power-down Standby Current:
All banks idle; Power-down mode; t_CK = t_CK (min); CKE ≤ V_IL(max); V_IN = V_REF for DQ, DQS and DM.
Precharge Floating Standby Current:
CS ≥ V_IH(min); All banks idle; CKE ≥ V_IH(min); t_CK = t_CK (min);
Address and other control inputs changing once per clock cycle; V_IN = V_REF for DQ, DQS, and DM.
Precharge Quiet Standby Current:
CS ≥ V_IH(min); All banks idle; CKE ≥ V_IH(min); t_CK = t_CK (min);
Address and other control inputs stable at ≥ V_IH(min) or ≤ V_IL(max); V_IN = V_REF for DQ, DQS, and DM.
Active Power-down Standby Current:
One bank active; Power-down mode; CKE ≤ V_IL(max); t_CK = t_CK (min); V_IN = V_REF for DQ, DQS, and DM.
Active Standby Current:
CS ≥ V_IH(min); CKE ≥ V_IH(min); One bank active; t_RC = t_RAS (max); t_CK = t_CK (min);
DQ, DM, and DQS inputs changing twice per clock cycle;
Address and other control inputs changing once per clock cycle.
Operating Current (burst read):
BL = 2; Continuous burst reads; One bank active;
Address and control inputs changing once per clock cycle; t_CK = t_CK (min); I_OUT = 0mA;
50% of data changing on every transfer.
Operating Current (burst write):
BL = 2; Continuous burst writes; One bank active;
Address and control inputs changing once per clock cycle; t_CK = t_CK (min);
DQ, DM, and DQS inputs changing twice per clock cycle; 50% of input data changing at every transfer.
Auto Refresh Current:
t_RC = t_RFC(min)
Self Refresh Current:
CKE ≤ 0.2V; external clock on; t_CK = t_CK (min)
Operating Current (Four bank operation):
Four-bank interleaving READs (burst = 4) with auto precharge; t_RC = t_RC (min); t_CK = t_CK (min);
Address and control inputs change only during ACTIVE, READ, or WRITE commands; I_OUT = 0mA.
Notes:
1. Enable on-chip refresh and address counters.
2. Random address is changing; 50% of data is changing at every transfer.
Symbol
IDD0
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
IDD7
Note
2
1
2
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2011
Revision : 1.3
6/48