M13S128324A-2M Datasheet, PDF (2/48 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

ESMT
Functional Block Diagram
CLK
CLK
CKE
Clock
Generator
Address, BA
Mode Register &
Extended Mode
Register
Row
Address
Buffer
&
Refresh
Counter
CS
RAS
CAS
WE
Column
Address
Buffer
&
Refresh
Counter
M13S128324A (2M)
Bank D
Bank C
Bank B
Bank A
Sense Amplifier
Column Decoder
Data Control Circuit
DQS ^DM
DQ
CLK, CLK
DLL
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2011
Revision : 1.3
2/48