M13S128324A-2M Datasheet, PDF (31/48 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

ESMT
Timing Diagram
M13S128324A (2M)
Basic Timing (Setup, Hold and Access Time @ BL=4, CL=2)
CLK
CLK
CKE
0
1
2
3
4
5
6
7
8
9
10
tCH tCL
tCK
HIGH
tCH tCL
tCK
CS
RAS
tIS
tIH
CAS
BA0,BA1
BAa
A8/AP
Ra
ADDR
(A0~An)
Ra
WE
DQS
DQ
DM
COMMAND
ACTIVE
BAa
BAb
Ca
Cb
tDQSCK
tRPRE
tDQSCK
tRPST
Hi-Z
tDQSQ
tLZ
tAC _tHZ
Qa0 Qa1 Qa2 Qa3
tWPRES
Hi-Z
tQH
tDQSS
tDQSL
tDQSH
tWPRE
tDS tDH tDS tDH
Db0 Db1 Db2
tWPST
Db3
Hi-Z
Hi-Z
READ
WRITE
: Don’t care
10122B32R.B
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2011
Revision : 1.3
31/48