M13S128324A-2M Datasheet, PDF (38/48 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

ESMT
Write Interrupted by a Read (@ BL=8, CL=2)
0
1
CLK
CLK
CKE
2
3
4
5
HIGH
CS
RAS
CAS
BA0,BA1
BAa
BAb
A8/AP
ADDR
(A0~An)
Ca
Cb
WE
DQS
DQ
DM
COMMAND
Da0 Da1 Da2 Da3 Da4 Da5
WRITE
tWTR
READ
M13S128324A (2M)
6
7
8
9
10
Qb0 Qb1 Qb2 Qb3 Qb4 Qb5 Qb6 Qb6
: Don’t care
10122B32R.B
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2011
Revision : 1.3
38/48