M13S128324A-2M Datasheet, PDF (35/48 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

ESMT
M13S128324A (2M)
Write with Auto Precharge (@ BL=8)
0
1
CLK
CLK
CKE
2
3
4
5
6
7
8
9
10
HIGH
CS
RAS
CAS
BA0,BA1
BAa
BAa
A8/AP
ADDR
(A0~An)
WE
DQS
DQ
Ca
Da0 Da1 Da2 Da3 Da4 Da5 Da6 Da7
Ra
tWR
tDAL
Auto precharge start
Note1
tRP
DM
COMMAND
WRITE
Note: 1. The row active command of the precharge bank can be issued after t_RP from this point.
The new read/write command of another activated bank can be issued from this point.
At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.
ACTIVE
: Don’t care
10122B32R.B
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2011
Revision : 1.3
35/48