M13S128324A-2M Datasheet, PDF (37/48 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

ESMT
M13S128324A (2M)
Write Interrupted by Precharge & DM (@ BL=8)
0
1
CLK
CLK
2
3
4
0
1
2
3
4
5
CKE
HIGH
CS
RAS
CAS
BA0,BA1
BAa
BAa
BAb
BAc
A8/AP
ADDR
Ca
(A0~An)
WE
Cb
Cc
DQS
DQ
DM
COMMAND
Da0 Da1 Da2 Da3 Da4 Da5 Da6 Da7
Db0 Db1 Dc0 Dc1 Dc2 Dc3
WRITE
PRE
CHARGE
tCCD
WRITE
WRITE
: Don’t care
10122B32R.B
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2011
Revision : 1.3
37/48