M13S128324A-2M Datasheet, PDF (12/48 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

ESMT
M13S128324A (2M)
Command Truth Table
COMMAND
CKEn-1 CKEn _CS
RAS
CAS
WE
DM BA0~1
A8/AP
A11~A9,
A7~A0
Note
Register
Extended MRS
H
XLL
L
LX
OP CODE
1,2
Register
Mode Register Set
H
XLL
L
LX
OP CODE
1,2
Auto Refresh
H
3
H
LL
L
HX
X
Entry
L
3
Refresh
Self Refresh
LH
H
H
3
Exit
L
H
X
X
HX
X
X
3
Bank Active & Row Addr.
H
XLL
H
HX
V
Row Address
Read & Auto Precharge Disable
Column
H
Address ^{Auto Precharge Enable}
XLH
L
HX
V
L
Column 4
Address
H
(A0~A7) ⁴
Write & Auto Precharge Disable
Column
H
Address ^{Auto Precharge Enable}
XLH
L
LV
V
L
Column 4,8
Address
H
(A0~A7) ^4,6,8
Burst Terminate
H
XLH
H
LX
X
7
Precharge
Bank Selection
All Banks
V
L
H
XLL
H
LX
X
H
X
5
HX
X
X
Entry
H
L
X
Active Power Down Mode
LH
H
H
X
Exit
L
HXX
X
XX
HX
X
X
Entry
H
L
X
Precharge Power Down
Mode
LH
H
H
X
HX
X
X
Exit
L
H
X
LH
H
H
Deselect (NOP)
HX
X
X
H
X
X
X
No Operation (NOP)
LH
H
H
Notes:
(V = Valid, X = Don’t Care, H = Logic High, L = Logic Low)
1. OP Code: Operand Code. A0~A11 & BA0~BA1: Program keys. (@EMRS/MRS)
2. EMRS/MRS can be issued only at all banks precharge state.
A new command can be issued 2 clock cycles after EMRS or MRS.
3. Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by “Auto”.
Auto/self refresh can be issued only at all banks precharge state.
4. BA0~BA1: Bank select addresses.
If both BA0 and BA1 are “Low” at read, write, row active and precharge, bank A is selected.
If BA0 is “High” and BA1 is “Low” at read, write, row active and precharge, bank B is selected.
If BA0 is “Low” and BA1 is “High” at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are “High” at read, write, row active and precharge, bank D is selected.
5. If A8/AP is “High” at row precharge, BA is ignored and all banks are selected.
6. During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at t_RP after end of burst.
7. Burst Terminate command is valid at every burst length.
8. DM and Data-in are sampled at the rising and falling edges of the DQS. Data-in byte are masked if the corresponding and
coincident DM is “High”. (Write DM latency is 0).
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2011
Revision : 1.3
12/48