M13S128324A-2M Datasheet, PDF (10/48 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

ESMT
M13S128324A (2M)
AC Timing Parameter & Specifications - continued
Parameter
Symbol
-3.6
Min Max
-4
Min Max
-5
Min Max
-6
Unit Note
Min Max
Active to Precharge command
Active to Active /Auto Refresh
command period
t_RAS
39.6 70K 40 70K 40 70K 42
70K ns
t_RC
54
52
55
60
ns
Auto Refresh to Active /Auto Refresh
command period
t_RFC
64.8
68
70
72
ns
Active to Read delay
t_RCDRD 14.4
15
15
18
ns
Active to Write delay
t_RCDWR
10
10
10
18
ns
Precharge command period
t_RP
14.4
15
15
18
ns
Active to Read with Auto Precharge
command
t_RAP
t_RCDRD or
t_RAS min
t_RCDRD or
t_RAS min
t_RCDRD or
t_RAS min
t_RCDRD or
t_RAS min
ns
Active bank A to Active bank B
command
t_RRD
10
10
10
12
ns
Write recovery time
t_WR
15
15
15
15
ns
Write data in to Read command delay t_WTR
2
2
2
2
t_CK
Col. Address to Col. Address delay
t_CCD
1
1
1
1
t_CK
Average periodic refresh interval
t_REFI
7.8
7.8
7.8
7.8 us 14
Write preamble
t_WPRE
0.25
0.25
0.25
0.25
t_CK
Write postamble
t_WPST
0.4 0.6 0.4 0.6 0.4 0.6 0.4
0.6 t_CK
12
Read preamble
t_RPRE
0.9 1.1 0.9 1.1 0.9 1.1 0.9
1.1 t_CK
Read postamble
t_RPST
0.4 0.6 0.4 0.6 0.4 0.6 0.4
0.6 t_CK
Clock to DQS write preamble setup
time
t_WPRES
0
0
0
0
ns 13
Mode Register Set command cycle
time
t_MRD
2
2
2
2
t_CK
Exit self refresh to Read command
t_XSRD
200
200
200
200
t_CK
Exit self refresh to non-Read
command
t_XSNR
75
75
75
75
ns
Auto Precharge write recovery +
precharge time
t_DAL
(t_WR/t_CK)
+(t_RP/t_CK)
(t_WR/t_CK)
+(t_RP/t_CK)
(t_WR/t_CK)
+(t_RP/t_CK)
(t_WR/t_CK)
+(t_RP/t_CK)
t_CK
23
Notes:
1.
2.
3.
All voltages referenced to V_SS.
Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply
voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified.
The below figure represents the timing reference load used in defining the relevant timing parameters of the part. It is not
intended to be either a precise representation of the typical system environment nor a depiction of the actual load
presented by a production tester. System designers will use IBIS or other simulation tools to correlate the timing reference
load to a system environment. Manufacturers will correlate to their production test conditions (generally a coaxial
transmission line terminated at the tester electronics).
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2011
Revision : 1.3
10/48