M13S128324A-2M Datasheet, PDF (44/48 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

ESMT
Mode Register Set
CLK
CLK
0
1
CKE
CS
RAS
2
3
4
5
6
tMRD
HIGH
CAS
WE
BA0,BA1
A8/AP
ADDR
(A0~An)
ADDRESS KEY
DS
DQ
DQS
tRP
High-Z
High-Z
Precharge
Command
All Bank
Mode Register Set
Command
Any
Command
Note: Power & Clock must be stable for 200us before precharge all banks.
M13S128324A (2M)
7
8
9
10
: Don’t care
10122B32R.B
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2011
Revision : 1.3
44/48