M13S128324A-2M Datasheet, PDF (32/48 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

ESMT
Multi Bank Interleaving READ (@ BL=4, CL=2)
0
1
2
3
4
5
CLK
CLK
CKE
HIGH
M13S128324A (2M)
6
7
8
9
10
CS
RAS
CAS
BA0,BA1
BAa
BAb
BAa
BAb
A8/AP
Ra
Rb
ADDR
Ra
Rb
Ca
Cb
(A0~An)
WE
DQS
DQ
DM
COMMAND
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3
ACTIVE
tRCDRD
tRRD
ACTIVE
READ
tCCD
READ
: Don’t care
10122B32R.B1
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2011
Revision : 1.3
32/48