M13S128324A-2M Datasheet, PDF (16/48 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

ESMT
M13S128324A (2M)
Burst
Length
2
4
8
Burst Address Ordering for Burst Length
Starting
Address (A2, A1, A0)
xx0
xx1
x00
x01
x10
x11
000
001
010
011
100
101
110
111
Sequential Mode
0, 1
1, 0
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 4, 5, 6, 7, 0
2, 3, 4, 5, 6, 7, 0, 1
3, 4, 5, 6, 7, 0, 1, 2
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 0, 1, 2, 3, 4
6, 7, 0, 1, 2, 3, 4, 5
7, 0, 1, 2, 3, 4, 5, 6
Interleave Mode
0, 1
1, 0
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
DLL Enable / Disable
The DLL must be enabled for normal operation. DLL enable is required during power-up initialization, and upon returning to
normal operation after having disabled the DLL for the purpose of debug or evaluation (upon exiting Self Refresh Mode, the
DLL is enabled automatically). Any time the DLL is enabled, 200 clock cycles must occur before a READ command can be
issued.
Output Drive Strength
The normal drive strength for all outputs is specified to be SSTL_2, Class II. The device also support reduced drive strength
options, intended for lighter load and/or point-to-point environments.
0
1
CLK
CLK
Mode Register
2
3
4
5
6
7
COMMAND
Precharge
All Banks
tCK
t *2
RP
*1
MRS / EMRS
tMRD
Any
Command
*1: MRS/EMRS can be issued only at all banks precharge state.
*2: Minimum t_RP is required to issue MRS/EMRS command.
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2011
Revision : 1.3
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