M13S128324A-2M Datasheet, PDF (11/48 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

ESMT
M13S128324A (2M)
4. AC timing and IDD tests may use a V_IL to V_IH swing of up to 1.5 V in the test environment, but input timing is still referenced
to V_REF (or to the crossing point for CLK/ CLK ), and parameter specifications are guaranteed for the specified AC input
levels under normal use conditions. The minimum slew rate for the input signals is 1 V/ns in the range between V_IL(AC) and
V_IH(AC).
5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch
as a result of the signal crossing the AC input level and will remain in that state as long as the signal does not ring back
above (below) the DC input LOW (HIGH) level.
6. Inputs are not recognized as valid until V_REF stabilizes. Exception: during the period before V_REF stabilizes, CKE ≤ 0.2V_DDQ
is recognized as LOW.
7. Enables on-chip refresh and address counters.
8. IDD specifications are tested after the device is properly initialized.
9. The CLK/ CLK input reference level (for timing referenced to CLK/ CLK ) is the point at which CLK and CLK cross; the
input reference level for signals other than CLK/ CLK , is V_REF.
10. The output timing reference voltage level is V_TT.
11. t_HZ and t_LZ transitions occur in the same access time windows as valid data transitions. These parameters are not
referenced to a specific voltage level but specify when the device output is no longer driving (t_HZ), or begins driving (t_LZ).
12. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter,
but system performance (bus turnaround) will degrade accordingly.
13. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this CLK
edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no
writes were previously in progress on the bus, DQS will be transitioning from High- Z to logic LOW. If a previous write was
in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on t_DQSS.
14. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.
15. For command/address input slew rate ≥ 1.0 V/ns
16. For command/address input slew rate ≥ 0.5 V/ns and < 1.0 V/ns
17. For CLK & CLK slew rate ≥ 1.0 V/ns
18. These parameters guarantee device timing, but they are not necessarily tested on each device. They may be guaranteed
by device design or tester correlation.
19. Slew Rate is measured between V_OH(AC) and V_OL(AC).
20. Min (t_CL, t_CH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e.
this value can be greater than the minimum specification limits for t_CL and t_CH).....For example, t_CL and t_CH are = 50% of the
period, less the half period jitter (t_JIT(HP)) of the clock source, and less the half period jitter due to crosstalk (t_JIT(crosstalk))
into the clock traces.
21. t_QH = t_HP - t_QHS, where:
t_HP = minimum half clock period for any given cycle and is defined by clock high or clock low (t_CH, t_CL). t_QHS accounts for 1)
The pulse duration distortion of on-chip clock circuits; and 2) The worst case push-out of DQS on one transition followed
by the worst case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output
pattern effects, and p-channel to n-channel variation of the output drivers.
22. t_DQSQ Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for
any given cycle.
23. For each of the terms above, if not already an integer, round to the next highest integer.
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2011
Revision : 1.3
11/48