M13S128324A-2M Datasheet, PDF (34/48 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

ESMT
M13S128324A (2M)
Read with Auto Precharge (@ BL=8)
0
1
CLK
CLK
CKE
2
3
4
5
6
7
8
9
10
HIGH
CS
RAS
CAS
BA0,BA1
BAa
A8/AP
ADDR
Ca
(A0~An)
WE
DQS(CL=2)
DQ(CL=2)
DQS(CL=2.5)
DQ(CL=2.5)
BAa
Ra
Auto precharge start
tRP
Note1
Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 Qa6 Qa7
Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 Qa6 Qa7
DM
COMMAND
READ
ACTIVE
Note: 1. The row active command of the precharge bank can be issued after t_RP from this point.
The new read/write command of another activated bank can be issued from this point.
At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.
: Don’t care
10122B32R.B
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2011
Revision : 1.3
34/48