M13S5121632A-2S Datasheet, PDF (8/48 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

ESMT
M13S5121632A (2S)
AC Operation Conditions & Timing Specifications
AC Operation Conditions
Parameter
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals
Input Differential Voltage, CLK and CLK inputs
Symbol
V_IH(AC)
V_IL(AC)
V_ID(AC)
Min
V_REF + 0.31
0.7
Max
V_REF - 0.31
V_DDQ+0.6
Unit
V
V
V
Note
1
Input Crossing Point Voltage, CLK and CLK inputs
V_IX(AC) 0.5*V_DDQ-0.2 0.5*V_DDQ+0.2
V
2
Notes:
1. V_ID is the magnitude of the difference between the input level on CLK and the input on CLK .
2. The value of V_IX is expected to equal 0.5*V_DDQ of the transmitting device and must track variations in the DC level of
the same.
AC Overshoot / Undershoot Specification
Parameter
Pin
Maximum peak amplitude allowed for overshoot
Maximum peak amplitude allowed for undershoot
Maximum overshoot area above V_DD
Maximum undershoot area below V_SS
Address, Control
Data, Strobe, Mask
Address, Control
Data, Strobe, Mask
Address, Control
Data, Strobe, Mask
Address, Control
Data, Strobe, Mask
Value
-5 / -6
1.5
1.2
1.5
1.2
4.5
2.4
4.5
2.4
Unit
V
V
V
V
V-ns
V-ns
V-ns
V-ns
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2014
Revision : 1.1
8/48