M13S5121632A-2S Datasheet, PDF (20/48 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

ESMT
M13S5121632A (2S)
Read Interrupted by a Precharge
A Burst Read operation can be interrupted by precharge of the same bank. The minimum 1 clock is required for the read to
precharge intervals. A precharge command to output disable latency is equivalent to the CAS latency.
<Burst Length = 8, CAS Latency = 3>
0
1
CLK
2
3
CLK
1tCK
COMMAND
READ
Precharge
NOP
NOP
4
NOP
5
6
7
NOP
NOP
NOP
8
NOP
DQS
DQ's
DOUT 0 DOUT 1 DOUT 2 DOUT 3 DOUT 4 DOUT 5 DOUT 6 DOUT 7
Interrupted by precharge
When a burst Read command is issued to a DDR SDRAM, a Precharge command may be issued to the same bank before
the Read burst is complete. The following functionality determines when a Precharge command may be given during a Read
burst and when a new Bank Activate command may be issued to the same bank.
1. For the earliest possible Precharge command without interrupting a Read burst, the Precharge command may be given on
the rising clock edge which is CL clock cycles before the end of the Read burst where CL is the CAS Latency. A new
Bank Activate command may be issued to the same bank after t_RP (RAS precharge time).
2. When a Precharge command interrupts a Read burst operation, the Precharge command may be given on the rising clock
edge which is CL clock cycles before the last data from the interrupted Read burst where CL is the CAS Latency. Once
the last data word has been output, the output buffers are tristated. A new Bank Activate command may be issued to the
same bank after t_RP.
3. For a Read with auto precharge command, a new Bank Activate command may be issued to the same bank after t_RP
where t_RP begins on the rising clock edge which is CL clock cycles before the end of the Read burst where CL is the CAS
Latency. During Read with auto precharge, the initiation of the internal precharge occurs at the same time as the earliest
possible external Precharge command would initiate a precharge operation without interrupting the Read burst as
described in 1 above.
4. For all cases above, t_RP is an analog delay that needs to be converted into clock cycles. The number of clock cycles
between a Precharge command and a new Bank Activate command to the same bank equals t_RP / t_CK (where t_CK is the
clock cycle time) with the result rounded up to the nearest integer number of clock cycles.
In all cases, a Precharge operation cannot be initiated unless t_RAS (min) [minimum Bank Activate to Precharge time] has been
satisfied. This includes Read with auto precharge commands where t_RAS (min) must still be satisfied such that a Read with
auto precharge command has the same timing as a Read command followed by the earliest possible Precharge command
which does not interrupt the burst.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2014
Revision : 1.1
20/48