M13S5121632A-2S Datasheet, PDF (33/48 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

ESMT
M13S5121632A (2S)
Multi Bank Interleaving WRITE (@ BL=4)
0
1
CLK
CLK
2
3
4
5
6
7
8
9
10
CKE
HIGH
CS
RAS
CAS
BA0,BA1
A10/AP
ADDR
(A0~An)
WE
DQS
DQ
DM
COMMAND
BAa
BAb
BAa
BAb
Ra
Rb
Ra
Rb
Ca
Cb
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3
ACTIVE
tRCD
tRRD
ACTIVE
WRITE
tRCD
tCCD
WRITE
: Don’t care
10122B16R.B
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2014
Revision : 1.1
33/48