M13S5121632A-2S Datasheet, PDF (38/48 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

ESMT
Write Interrupted by a Read (@ BL=8, CL= 3)
0
1
2
3
4
5
CLK
CLK
CKE
HIGH
CS
RAS
CAS
BA0,BA1
BAa
BAb
A10/AP
ADDR
(A0~An)
Ca
Cb
WE
DQS
DQ
DM
COMMAND
Da0 Da1 Da2 Da3 Da4 Da5
WRITE
tWTR
READ
M13S5121632A (2S)
6
7
8
9
10
Qb0 Qb1 Qb2 Qb3 Qb4 Qb5
: Don’t care
10122B16R.B1
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2014
Revision : 1.1
38/48