M13S5121632A-2S Datasheet, PDF (41/48 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

ESMT
Read Interrupted by a Read (@ BL=8, CL=3)
0
1
2
3
4
5
CLK
CLK
CKE
HIGH
CS
RAS
CAS
BA0,BA1
A10/AP
BAa
BAb
ADDR
(A0~An)
WE
Ca
Cb
M13S5121632A (2S)
6
7
8
9
10
DQS
DQ
DM
COMMAND
tCCD
READ
READ
Qa0 Qa1 Qb0 Qb1 Qb2 Qb3 Qb4 Qb5 Qb6 Qb7
: Don’t care
10122B16R.B1
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2014
Revision : 1.1
41/48