M13S5121632A-2S Datasheet, PDF (10/48 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

ESMT
M13S5121632A (2S)
AC Timing Parameter & Specifications – continued
Parameter
Active to Precharge command
Active to Active / Auto Refresh
command period
Auto Refresh to Active / Auto Refresh
command period
Active to Read, Write delay
Precharge command period
Active to Read with Auto Precharge
command
Active bank A to Active bank B
command
Write recovery time
Write data in to Read command delay
Average periodic refresh interval
Write preamble
Write postamble
Read preamble
Read postamble
Clock to DQS write preamble setup time
Mode Register Set command cycle time
Exit self refresh to Read command
Exit self refresh to non-Read command
Auto Precharge write recovery +
precharge time
Symbol
t_RAS
t_RC
t_RFC
t_RCD
t_RP
t_RAP
t_RRD
t_WR
t_WTR
t_REFI
t_WPRE
t_WPST
t_RPRE
t_RPST
t_WPRES
t_MRD
t_XSRD
t_XSNR
t_DAL
-5
min
max
40
70K
55
70
15
15
15
10
15
2
7.8
0.25
0.4
0.6
0.9
1.1
0.4
0.6
0
2
200
75
(t_WR/t_CK)
+
(t_RP/t_CK)
-6
min
max
42
70K
60
72
18
18
18
12
15
2
7.8
0.25
0.4
0.6
0.9
1.1
0.4
0.6
0
2
200
75
(t_WR/t_CK)
+
(t_RP/t_CK)
Unit Note
ns
ns
ns
ns
ns
ns
ns
ns
t_CK
us
14
t_CK
t_CK
12
t_CK
t_CK
ns
13
t_CK
t_CK
ns
t_CK
23
Notes:
1.
2.
3.
All voltages referenced to V_SS.
Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply
voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified.
The below figure represents the timing reference load used in defining the relevant timing parameters of the part. It is
not intended to be either a precise representation of the typical system environment nor a depiction of the actual load
presented by a production tester. System designers will use IBIS or other simulation tools to correlate the timing
reference load to a system environment. Manufacturers will correlate to their production test conditions (generally a
coaxial transmission line terminated at the tester electronics).
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2014
Revision : 1.1
10/48