M13S5121632A-2S Datasheet, PDF (21/48 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

ESMT
M13S5121632A (2S)
Write Interrupted by a Write
A Burst Write can be interrupted before completion of the burst by a new Write command, with the only restriction that the
interval that separates the commands must be at least one clock cycle. When the previous burst is interrupted, the remaining
addresses are overridden by the new address and data will be written into the device until the programmed burst length is
satisfied.
<Burst Length = 4>
C LK
C LK
COMMAND
0
N OP
1
2
1 tCK
W RIT E A W R IT E B
3
N OP
4
NO P
5
6
7
8
NOP
N OP
NOP
NOP
DQS
Hi -Z
DQ 's
Hi- Z
DI N A 0 D IN A1 D IN B0 DI N B1 D I N B 2 DI N B 3
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2014
Revision : 1.1
21/48