M13S5121632A-2S Datasheet, PDF (36/48 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

ESMT
M13S5121632A (2S)
Write followed by Precharge (@ BL=4)
0
1
CLK
CLK
2
3
4
5
6
7
8
9
10
CKE
HIGH
CS
RAS
CAS
BA0,BA1
A10/AP
ADDR
(A0~An)
WE
DQS
DQ
DM
COMMAND
BAa
Ca
Da0 Da1 Da2 Da3
WRITE
BAa
tWR
PRE
CHARGE
: Don’t care
10122B16R.B
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2014
Revision : 1.1
36/48