M13S5121632A-2S Datasheet, PDF(3/48 Page) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

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M13S5121632A-2S Datasheet, PDF (3/48 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

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ESMT

PIN CONFIGURATION (TOP VIEW)

(TSOPII 66L, 400milX875mil Body, 0.65mm Pin Pitch)

M13S5121632A (2S)

Pin Description

Pin Name

A0~A12,

BA0, BA1

Function

Address inputs

- Row address A0~A12

- Column address A0~A9

A10/AP: AUTO Precharge

BA0, BA1: Bank selects (4 Banks)

Pin Name

Function

LDM, UDM

DM is an input mask signal for write data.

LDM corresponds to the data on DQ0~DQ7;

UDM correspond to the data on DQ8~DQ15.

DQ0~DQ15 Data-in/Data-out

CLK, CLK Clock input

RAS

Row address strobe

CAS

Column address strobe

Write enable

VSS

Ground

VDD

LDQS, UDQS

Power

Bi-directional Data Strobe.

LDQS corresponds to the data on DQ0~DQ7;

UDQS correspond to the data on DQ8~DQ15.

CKE

VDDQ

VSSQ

VREF

Clock enable

Chip select

Supply Voltage for DQ

Ground for DQ

Reference Voltage for SSTL_2

No connection

Elite Semiconductor Memory Technology Inc.

Publication Date : Jul. 2014

Revision : 1.1

3/48

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