M13S5121632A-2S Datasheet, PDF (26/48 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

ESMT
M13S5121632A (2S)
Write with Auto Precharge
If A10 is high when write command is issued, the write with auto-precharge function is performed. Any new command to the
same bank should not be issued until the internal precharge is completed. The internal precharge begins at the rising edge of
the CLK with the t_WR delay after the last data-in.
<Burst Length = 4>
0
1
CLK
CLK
COMMAND
Bank A
ACTIVE
NOP
2
3
4
NOP
Write A
Auto Precharge
NOP
5
6
7
8
NOP
NOP
NOP
NOP
DQS
DQ's
DIN 0 DIN 1 DIN 2 DIN 3
At burst read / write with auto precharge, CAS interrupt of the same bank is illegal.
*Bank can be reactivated
at completion of tRP
tWR
tRP
Internal precharge start
Asserted
Command
WRITE
WRITE with AP^*1
READ
READ with AP
Active
Precharge
4
WRITE
WRITE
with AP
Illegal
Illegal
Illegal
Illegal
For the same bank
5
6
7
WRITE Illegal
Illegal
WRITE
with AP
Illegal
Illegal
READ +
DM^*2
READ
with AP+
DM
Illegal
READ+
DM
READ
with AP+
DM
Illegal
READ
READ
with AP
Illegal
Illegal
Illegal
Illegal
Note: 1. AP = Auto Precharge
2. DM: Refer to “Write Interrupted by a Read & DM“
8
Illegal
Illegal
Illegal
Illegal
Illegal
Illegal
4
Legal
Legal
For the different bank
5
6
7
Legal Legal Legal
Legal Legal Legal
8
Legal
Legal
Illegal Illegal Illegal Legal Legal
Illegal Illegal Illegal Legal Legal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2014
Revision : 1.1
26/48