M13S5121632A-2S Datasheet, PDF (45/48 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

ESMT
Simplified State Diagram
Power
Applied
Power
On
M13S5121632A (2S)
0911R.A
Precharge
PREALL
MRS
EMRS
MRS
REFS
Self
Refresh
REFSX
Idle
REFA
Auto
Refresh
CKEL
CKEH
Active
Power
Down
ACT
Precharge
Power
Down
Write
Write
CKEH
CKEL
Write
Bank
Active
Burst Stop
Read
Read
Write A
Read A
Read
Read
Write A
Write
A
PRE
PRE
Read A
PRE
PRE
Precharge
PREALL
Read A
Read
A
Automatic Sequence
Command Sequence
PREALL = Precharge All Banks
MRS = Mode Register Set
EMRS = Extended Mode Register Set
REFS = Enter Self Refresh
REFSX = Exit Self Refresh
REFA = Auto Refresh
CKEL = Enter Power Down
CKEH = Exit Power Down
ACT = Active
Write A = Write with Autoprecharge
Read A = Read with Autoprecharge
PRE = Precharge
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2014
Revision : 1.1
45/48