M13S5121632A-2S Datasheet, PDF (47/48 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

ESMT
Revision History
Revision
0.1
1.0
1.1
Date
2013.12.24
2014.06.18
2014.07.17
M13S5121632A (2S)
Description
Original
1. Delete "Preliminary"
2. Delete speed grade -4
Modify Input / Output Capacitance
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2014
Revision : 1.1
47/48