M13S5121632A-2S Datasheet, PDF (17/48 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

ESMT
M13S5121632A (2S)
Precharge
The precharge command is used to precharge or close a bank that has activated. The precharge command is issued when CS ,
RAS and WE are low and CAS is high at the rising edge of the clock. The precharge command can be used to precharge
each bank respectively or all banks simultaneously. The bank select addresses (BA0, BA1) are used to define which bank is
precharged when the command is initiated. For write cycle, t_WR(min) must be satisfied until the precharge command can be
issued. After t_RP from the precharge, an active command to the same bank can be initiated.
Burst Selection for Precharge by bank address bits
A10/AP
BA1
BA0
Precharge
0
0
0
Bank A Only
0
0
1
Bank B Only
0
1
0
Bank C Only
0
1
1
Bank D Only
1
X
X
All Banks
No Operation & Device Deselect
The device should be deselected by deactivating the CS signal. In this mode DDR SDRAM should ignore all the control inputs.
The DDR SDRAMs are put in NOP mode when CS is active and by deactivating RAS , CAS and WE . For both Deselect
and NOP the device should finish the current operation when this command is issued.
Bank / Row Active
The Bank Activation command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the
clock (CLK). The DDR SDRAM has four independent banks, so Bank Select addresses (BA0, BA1) are required. The Bank
Activation command must be applied before any Read or Write operation is executed. The Bank Activation command to the first
Read or Write command must meet or exceed the minimum of RAS to CAS delay time (t_RCD min). Once a bank has been
activated, it must be precharged before another Bank Activation command can be applied to the same bank. The minimum time
interval between interleaved Bank Activation command (Bank A to Bank B and vice versa) is the Bank to Bank delay time (t_RRD
min).
Bank Activation Command Cycle ( CAS Latency = 3)
0
1
CLK
CLK
2
3
Address
Bank A
Row Addr.
Command
Bank A
Activate
Bank A
Col. Addr.
RAS-CAS delay (tRCD)
NOP
NOP
Write A
with AP
ROW Cycle Time (tRC)
Tn
Tn+1
Tn+2
Bank B
Row Addr.
Bank A
Row. Addr.
RAS-RAS delay (tRRD)
Bank B
Activate
NOP
Bank A
Activate
: Don't Care
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2014
Revision : 1.1
17/48