M13S5121632A-2S Datasheet, PDF (25/48 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

ESMT
M13S5121632A (2S)
Read With Auto Precharge
If a read with auto precharge command is initiated, the DDR SDRAM automatically enters the precharge operation BL/2 clock
later from a read with auto precharge command when t_RAS (min) is satisfied. If not, the start point of precharge operation will be
delayed until t_RAS (min) is satisfied. Once the precharge operation has started the bank cannot be reactivated and the new
command can not be asserted until the precharge time (t_RP) has been satisfied.
<Burst Length = 4, CAS Latency = 2.5>
0
1
2
3
4
CLK
CLK
C O M M A N D _ABCaTnkIVAE
NOP
NOP
AutoRPeraedchAarge ^{N O P}
tRAS (min)
DQS
CAS Latency = 2.5
DQ's
Hi-Z
Hi-Z
Auto-Precharge starts
5
6
7
8
9
NOP
NOP
NOP
NOP
NOP
* Bank can be reactivated at
tRP
completion of precharge
DOUT 0 DOUT 1 DOUT 2 DOUT 3
When the Read with Auto Precharge command is issued, new command can be asserted at 4, 5 and 6 respectively as follow.
Asserted
Command
READ
READ with AP^*1
Active
Precharge
For the same bank
4
5
READ
Illegal
READ with AP
Illegal
Illegal
Illegal
Legal
Legal
6
Illegal
Illegal
Illegal
Illegal
Note 1: AP = Auto Precharge
For the different bank
4
5
6
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2014
Revision : 1.1
25/48