M13S5121632A-2S Datasheet, PDF (32/48 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

ESMT
M13S5121632A (2S)
Multi Bank Interleaving READ (@ BL=4, CL=3)
0
1
CLK
CLK
2
3
4
5
6
CKE
HIGH
CS
RAS
CAS
BA0,BA1
BAa
BAb
BAa
BAb
A10/AP
Ra
Rb
ADDR
Ra
Rb
Ca
Cb
(A0~An)
WE
DQS
DQ
DM
COMMAND
ACTIVE
tRCD
tRRD
ACTIVE
READ
tCCD
READ
7
8
9
10
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3
: Don’t care
10122B16R.B1
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2014
Revision : 1.1
32/48