M13S5121632A-2S Datasheet, PDF (44/48 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

ESMT
M13S5121632A (2S)
Mode Register Set
CLK
CLK
0
1
CKE
CS
RAS
2
3
4
5
6
7
8
tMRD
HIGH
9
10
CAS
WE
BA0,BA1
A10/AP
ADDR
(A0~An)
ADDRESS KEY
DS
DQ
DQS
tRP
High-Z
High-Z
Precharge
Command
All Bank
Mode Register Set
Command
Any
Command
Note: Power & Clock must be stable for 200us before precharge all banks.
: Don’t care
10122B16R.B
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2014
Revision : 1.1
44/48