M13S5121632A-2S Datasheet, PDF (14/48 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

ESMT
M13S5121632A (2S)
Mode Register Definition
Mode Register Set (MRS)
The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency,
addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for
variety of different applications. The default value of the register is not defined, therefore the mode register must be written after
EMRS setting for proper DDR SDRAM operation. The mode register is written by asserting low on CS , RAS , CAS , WE
and BA0~BA1 (The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the mode register).
The state of address pins A0~A12 in the same cycle as CS , RAS , CAS , WE and BA0~BA1 going low is written in the
mode register. Two clock cycles are requested to complete the write operation in the mode register. The mode register contents
can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle
state. The mode register is divided into various fields depending on functionality. The burst length uses A0~A2, addressing
mode uses A3, CAS latency (read latency from column address) uses A4~A6. A7 is used for test mode. A8 is used for DLL
reset. A7 must be set to low for normal MRS operation. Refer to the table for specific codes for various burst length, addressing
modes and CAS latencies.
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
0
0
RFU
DLL TM
CAS Latency
BT
Burst Length
Mode Register
A8 DLL Reset
0
No
1
Yes
A7
Mode
0
Normal
1
Test
A3 Burst Type
0
Sequential
1
Interleave
BA1
0
0
BA0
0
1
Operating Mode
MRS Cycle
EMRS Cycle
CAS Latency
A6 A5 A4
000
001
010
011
100
110
111
Latency
Reserved
Reserved
Reserved
3
4
2.5
Reserved
Note: RFU (Reserved for future use) must stay “0” during MRS cycle.
Burst Length
A2 A1 A0
Length
Sequential Interleave
0 0 0 Reserved Reserved
001
2
2
010
4
4
011
8
8
1 0 0 Reserved Reserved
1 0 1 Reserved Reserved
1 1 0 Reserved Reserved
1 1 1 Reserved Reserved
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2014
Revision : 1.1
14/48