M13S5121632A-2S Datasheet, PDF (31/48 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

ESMT
M13S5121632A (2S)
Timing Diagram
Basic Timing (Setup, Hold and Access Time @ BL=4, CL=3)
CLK
CLK
0
1
2
3
4
5
6
7
8
9
10
tCH tCL
tCK
tCH tCL
tCK
CKE
HIGH
CS
RAS
tIS
tIH
CAS
BA0,BA1
BAa
BAa
A10/AP
Ra
ADDR
(A0~An)
Ra
Ca
WE
DQS
DQ
DM
BAb
Cb
tDQSCK
tRPRE
tLZ
tDQSCK
tDQSQ
tAC
Qa0 Qa1 Qa2
tRPST
tDQSS
tDQSL
tDQSH
tWPRES
tHZ
tWPRE
tDS tDH tDS tDH
Qa3
Hi-Z
Db0 Db1
Db2
tWPST
Db3
tQH
Hi-Z
Hi-Z
COMMAND
ACTIVE
READ
WRITE
: Don’t care
10122B16R.B1
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2014
Revision : 1.1
31/48