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M13S5121632A-2S Datasheet, PDF (1/48 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle | |||
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ESMT
M13S5121632A (2S)
DDR SDRAM
8M x 16 Bit x 4 Banks
Double Data Rate SDRAM
Features
ï¬ Double-data-rate architecture, two data transfers per clock cycle
ï¬ Bi-directional data strobe (DQS)
ï¬ Differential clock inputs (CLK and CLK )
ï¬ DLL aligns DQ and DQS transition with CLK transition
ï¬ Four bank operation
ï¬ CAS Latency : 2.5, 3, 4
ï¬ Burst Type : Sequential and Interleave
ï¬ Burst Length : 2, 4, 8
ï¬ All inputs except data & DM are sampled at the rising edge of the system clock (CLK)
ï¬ Data I/O transitions on both edges of data strobe (DQS)
ï¬ DQS is edge-aligned with data for READs; center-aligned with data for WRITEs
ï¬ Data mask (DM) for write masking only
ï¬ VDD = 2.5V ± 0.2V, VDDQ = 2.5V ± 0.2V
ï¬ 7.8us refresh interval
ï¬ Auto & Self refresh
ï¬ 2.5V I/O (SSTL_2 compatible)
Ordering Information
Product ID
Max Freq.
M13S5121632A -5TG2S
200MHz (DDR400)
M13S5121632A -6TG2S
166MHz (DDR333)
VDD
2.5V
Package
66 pin TSOPII
Comments
Pb-free
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2014
Revision : 1.1
1/48
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