M13S5121632A-2S Datasheet, PDF (7/48 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

ESMT
IDD Specifications
Symbol
IDD0
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
IDD7
Version
-5
-6
90
80
110
100
8
8
50
50
50
50
45
40
80
70
130
120
130
120
140
130
6
6
220
210
M13S5121632A (2S)
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Input / Output Capacitance
Parameter
Package Symbol
Min
Input capacitance (A0~A12, BA0~BA1,
CKE, CS , RAS , CAS , WE )
TSOP
C_IN1
3
Input capacitance (CLK, CLK )
TSOP
C_IN2
4
Max
Delta Cap
(max)
Unit
Note
5.5
0.5
pF 1,4
5
0.25
pF 1,4
Data & DQS input/output capacitance
TSOP
C_OUT
2
5.5
0.5
pF 1,2,3,4
Input capacitance (DM)
TSOP
C_IN3
3
5
0.5
pF 1,2,3,4
Notes:
1. These values are guaranteed by design and are tested on a sample basis only.
2. Although DM is an input -only pin, the input capacitance of this pin must model the input capacitance of the DQ and
DQS pins. This is required to match signal propagation times of DQ, DQS, and DM in the system.
3. Unused pins are tied to ground.
4. This parameter is sampled. V_DDQ = 2.5V ± 0.2V, V_DD = 2.5V ± 0.2V. f=100MHz, T_A =25°C, V_OUT(DC) = V_DDQ/2, V_OUT
(peak to peak) = 0.2V. DM inputs are grouped with I/O pins - reflecting the fact that they are matched in loading (to
facilitate trace matching at the board level).
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2014
Revision : 1.1
7/48