M13S5121632A-2S Datasheet, PDF (16/48 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

ESMT
M13S5121632A (2S)
Burst
Length
2
4
8
Burst Address Ordering for Burst Length
Starting
Address (A2, A1, A0)
Sequential Mode
xx0
0, 1
xx1
1, 0
x00
0, 1, 2, 3
x01
1, 2, 3, 0
x10
2, 3, 0, 1
x11
3, 0, 1, 2
000
0, 1, 2, 3, 4, 5, 6, 7
001
1, 2, 3, 4, 5, 6, 7, 0
010
2, 3, 4, 5, 6, 7, 0, 1
011
3, 4, 5, 6, 7, 0, 1, 2
100
4, 5, 6, 7, 0, 1, 2, 3
101
5, 6, 7, 0, 1, 2, 3, 4
110
6, 7, 0, 1, 2, 3, 4, 5
111
7, 0, 1, 2, 3, 4, 5, 6
Interleave Mode
0, 1
1, 0
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
DLL Enable / Disable
The DLL must be enabled for normal operation. DLL enable is required during power-up initialization, and upon returning
to normal operation after having disabled the DLL for the purpose of debug or evaluation (upon exiting Self Refresh Mode,
the DLL is enabled automatically). Any time the DLL is enabled, 200 clock cycles must occur before a READ command
can be issued.
Output Drive Strength
The normal drive strength for all outputs is specified to be SSTL_2, Class II. The device also support reduced drive
strength options, intended for lighter load and/or point-to-point environments.
0
1
CLK
CLK
Mode Register
2
3
4
5
6
7
COMMAND
Precharge
All Banks
tCK
t R P^{* 2}
*1
MRS / EMRS
tMRD
Any
Command
*1: MRS/EMRS can be issued only at all banks precharge state.
*2: Minimum t_RP is required to issue MRS/EMRS command.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2014
Revision : 1.1
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